Famicom cartridge technical information - Bandai BA-JUMP2

概要

BA-JUMP2 はファミコンジャンプIIのカートリッジ内の基板の名称。
ドラゴンクエストIVと開発会社が同じなのか、ゲームの見た目やハードウェアの仕様もそれに似ているところが多い。
メモリコントローラが当時のバンダイ製造のカートリッジと同じなのだが、Program ROM A18 の扱いが変なので、エミュレーションに成功するまで混乱があってその名残がいまでも続く。

wiring infomation

PCB

  • name: BA-JUMP2
  • device: LZ93D50, Program ROM, Charcter RAM, battery, Work RAM

memory controller

[label]
BANDAI
LZ93D50
9129 5 D

[pinout]
shrink-DIP 52pin
 1 ?                   |52 s? +5V
 2 ?                   |51 o  CPU $6000-$7fff enable#
 3 o program ROM EN#   |50 ?  ?
 4 s?+5V               |49 s? +5V
 5 i CPU PHI2          |48 ?  ?
 6 i CPU A13           |47 o  program ROM A17
 7 i CPU A14           |46 o  program ROM A15
 8 i CPU A3            |45 o  program ROM A14
 9 i CPU A2            |44 o  program ROM A16
10 i CPU A1            |43 i  CPU D7
11 i CPU A0            |42 i  CPU D6
12 i CPU ROMSEL#       |41 i  CPU D5
13 i CPU D0            |40 io CPU D4
14 i CPU D1            |39 i  CPU D3
15 i CPU D2            |38 o  CPU IRQ#
16 i CPU R/W           |37 o  VRAM A10
17 i PPU RD#           |36 o  NC
18 o NC (chr ROM A15)  |35 o  NC
19 o NC (chr ROM A12)  |34 o  NC
20 i PPU A10           |33 o  NC
21 i PPU A11           |32 o  NC
22 i GND (PPU A12)     |31 o  program ROM A18 (charcter ROM A10)
23 i GND (PPU A13)     |30 o  NC (charcter ROM EN#)
24 s GND               |29 i? GND
25 ?                   |28 o  work RAM enable (I2C SCL)
26 s GND               |27 IO NC (I2C SDA)

[logical assignments]
CPU PHI2 = CPU PHI2
CPU R/W = CPU R/W
CPU ROMSEL# = CPU ROMSEL#
CPU A14:13 = CPU A14:13
CPU D7:0 = CPU D7:0

PPU A13:12 = 2'b00
PPU A11:10 = PPU A11:10
固定値の以外の入力元は全て card edge

card edge connector

[logical assignments]
CPU IRQ# = CPU IRQ# (from LZ93D50)
VRAM A10 = VRAM 10 (from LZ93D50)
VRAM CS = PPU A13#
Sound in = Sound out
主要な配線のみ記載。

program ROM

[label]
NEC JAPAN
D23C4001EACZ W22
9149EY700

[logical assignments]
A18 = charcter ROM A10
A17:14 = program ROM A17:14
A13:0 = CPU A13:0
CE# = GND
OE# = program ROM EN#
D7:0 = CPU D7:0
pinout は 27C4001 互換。

work RAM

[label]
LH5160YF-10L
SHARP JAPAN
B046 R3BB

[logical assignments]
A12:0 = CPU A12:0
CS1# = CPU $6000-$7fff enable#
CS2 = I2C SCL
WE# = CPU R/W
OE# = GND
D7:0 = CPU D7:0
Vcc is connected battery backup supply

charcter RAM

[label]
LH5160YF-10L
SHARP JAPAN
B046 R3BB

[logical assignments]
A12:0 = PPU A12:0
CS1# = PPU A13
CS2 = +5V
WE# = PPU WR#
OE# = PPU RD#
D7:0 = PPU D7:0

software specification

memory map

[CPU - read]
$6000       I2C and external device input
$6001-$7fff 上記 の mirror
$6000-$7fff work RAM (battery backup, アドレス重複)
$8000-$bfff Program ROM bank #0 (switchable)
$c000-$ffff Program ROM bank #1 (half-fixed)

[CPU - write]
$6000-$7fff work RAM (battery backup)
$8000 Charcter ROM bank #0 register (program ROM A18)
$8001 Charcter ROM bank #1 register (program ROM A18)
$8002 Charcter ROM bank #2 register (program ROM A18)
$8003 Charcter ROM bank #3 register (program ROM A18)
$8008 Program ROM bank #0 register (program ROM A17:14)
$8009 Nametable register
$800a IRQ control register
$800b IRQ countner register #0
$800c IRQ countner register #1
$800d I2C control port (work RAM enable)
$800e-$800f おそらく未定義で未使用
$8010-$ffff $8000-$800f の mirror

[PPU - read/write]
0x0000-0x1fff charcter RAM on cartridge
0x2000-0x2fff FCG-1 と同じ

register

[I2C and external device input]
address: $6000 (read)
bit assignments
----------------
4   I2C SDA input (value 0)
$800d bit7 = 1, bit5 = 0 と設定すると値が読めるが、open drain の pin に プルアップ抵抗がないので入力値は 0 固定。

[Charcter ROM bank #0-#3 register]
address: $8000-$8003 (write)
bit assignments
----------------
0   program ROM address bit18
LZ93D50 への PPU A13:12 が 0 固定のため、register #4-#7 は無効。bit0 の出力は PPU A11:10 の入力に依存するので、出力を安定させるためには #0-#3 に全て同じ値を書き込むこと。

[Program ROM bank #0 register]
address: $8008 (write)
data bit assignments は FCG-1, FCG-2 と同じ

[Nametable register]
address: $8009 (write)
data bit assignments は FCG-1, FCG-2 と同じ
PPU A11:10 の入力は VRAM A10 への出力制御のために PPU A11:10 が配線されているので使用可能。その反面 program ROM A18 のレジスタが4つに増えている。

[IRQ xxx register]
address: $800a, $800b, $800c (write)
data bit assignments は FCG-1, FCG-2 と同じ

[I2C control/output port]
address: $800d (write)
bit assignments
----------------
7   SDA direction  0:write(must be set!), 1:read (bus-conflict)
5   work RAM CE2 0:disable, 1:enable
bit7 = 1, bit5 = 1 に設定すると、 CPU $6000-$7fff では LZ93D50 からの CPU D4 が出力となるので、 work RAM と D4 の出力が衝突する。このときの CPU からの read では内容が安定しないと思われる。

program bank switch の特記事項

[bank #0]
A18 = charcter ROM bank #0-#3 (PPU A11:10 に依存)
A17:14 = program ROM bank #0 register bit3:0
A13:0 = CPU A13:0

[bank #1]
A18 = charcter ROM bank #0-#3 (PPU A11:10 に依存)
A17:14 = 4'b1111
A13:0 = CPU A13:0
bank #1 の A17:14 は固定だが、 A18 は PPU A11:10 に依存する。CPU address に無関係。これは SUROM の bit 拡張と同じ。